In the past, liquid crystal displays using active matrix type liquid crystal panels included liquid crystal elements driven with alternating current (AC) by inverting the polarity of the applied data signals. This served to prevent deterioration of the liquid crystal elements. However, this caused noticeable screen flicker because all pixels were driven with the same polarity during the same frame. In these displays, in order to prevent flicker, the polarity of the two AC signals applied, respectively, to the adjacent pixels on every gate line and every data line are inverted.
FIG. 1 schematically illustrates the configuration of the liquid crystal panel of these conventional active matrix type liquid crystal displays. FIGS. 2 and 3 show drive waveforms which are applied to the liquid crystal panel of FIG. 1. In FIG. 1, the gate drive circuit 1 is connected to n lines of the row signal conductors G1 to Gn, and it sequentially supplies the drive waveform outputs shown in FIGS. 2a, 2b, and 3a to the row signal conductors G1 to Gn. A first data drive circuit 2 is connected to the odd numbered column signal conductors D1 to Dm-1, and supplies thereto the drive waveform outputs shown in FIGS. 2c and 3c. A second data drive circuit 3 is connected to the even numbered column signal conductors D2 to Dm, and it supplies to these lines the drive waveform outputs shown in FIGS. 2c and 3c. Thin film transistors 4 are placed at each point of crossing of the row and column conductors, with their gate and drain electrodes being connected, respectively, to row and column signal conductors, and their source electrodes being connected to pixels 5 as described below. Each pixel 5 is a liquid crystal cell, driven by its respective TFT 4.
The operation of the circuit of FIG. 1, using the drive waveforms of FIGS. 2 and 3, is as follows. First, the gate signals VGn and VGn+1 shown in FIGS. 2a and 2b, are applied sequentially to the gate electrodes of the respective TFT's 4 that are connected to the associated row signal conductor. This causes the row of TFT's 4 to be turned on. In synchronization with these gate signals, the data signals shown in FIG. 2c are sent by the first and second data drive circuits 2 and 3, and n pixels 5 connected to each column conductor are driven alternately with positive and negative polarity signals for every gate pulse applied to the row signal conductors. Thus, screen flicker is reduced. But m pixels 5 connected to the row signal conductors are not driven alternately each gate pulse as the aforementioned n number of pixels 5. Thus, flicker is not eliminated. To reduce flicker on pixels associated with every row signal conductor, the application of the first data signal VDm shown in FIG. 3b from the first data drive circuit 2 to the odd numbered column conductors, and the application of the second data signal VDm+1 shown in FIG. 3c from the second data drive circuit 3 to even numbered column conductors are synchronized with the output of the gate signal VGn shown in FIG. 3a from the gate drive circuit 1. Thus, the n pixels and the m pixels connected to each row and each column signal conductor, respectively, are driven alternately with positive and negative polarity. Flicker between each pixel is reduced.
Thus, in these conventional liquid crystal displays, as described above, the polarity of the voltage applied to the adjacent pixels on every row and column signal conductor is inverted in order to reduce screen flicker. However, the polarity reversal at every column signal conductor requires a high repetition frequency data signal, as shown in FIGS. 3b and 3c, thereby causing a high electric power consumption problem in the data drive circuit.
If an attempt is made to utilize a data signal having a high frequency and amplitude without reducing the output resistance of the data drive circuit, the output signal of the data drive circuit is considerably weakened. This affects the display data. Of course the output resistance of the data drive circuit can be reduced by enlarging the size of the output transistors. Accordingly, to avoid affecting the display data, the output resistance of the data drive circuit may be reduced, but this inevitably enlarges the chip size of the drive circuit, resulting in high cost.